API
- class acorechip.ACoreChip(*arg)
ACoreChip parameters and attributes
Parameters
- arg :
If any arguments are defined, the first one should be the parent instance
Attributes
- proplistlist
List of strings containing the names of attributes whose values are to be copied from the parent
- Rsfloat
Sampling rate [Hz] of which the input values are assumed to change. Default: 100.0e6
- IOSBundle
Members of this bundle are the IO’s of the entity. See documentation of thsdk package. Default members defined as
self.IOS.Members[‘A’]=IO() # Pointer for input data self.IOS.Members[‘control_write’]= IO() # Piter for control IO for rtl simulations
- add_simstop()
Adds logic to Verilog testbench that stops simulation when program runs to end.
- define_io_conditions()
This overloads the method called by run_rtl method. It defines the read/write conditions for the files
- init()
Method to re-initialize the structure if the attribute values are changed after creation.
- run(*arg)
The default name of the method to be executed. This means: parameters and attributes control what is executed if run method is executed. By this we aim to avoid the need of documenting what is the execution method. It is always self.run.
- class acorechip.acore_compilers.ACoreChiselCompiler(*arg, **kwargs)
Class for compiling Chisel to Verilog for A-Core
Parameters
- hw_config_pathstr
Path to A-Core hw config
- jtag_config_pathstr
Path to JTAG config
- chisel_dirstr
Location of A-Core chisel directory
- target_dirstr
Desired target directory for Verilog files
- gen_cheadersbool
Whether to generate C header files
- cheaders_target_dirstr
Path to desired target directory for C header files
- make_argsdict
Arbitrary make parameters to propagate
- skip_cleanbool
Skip make clean. Default False.
- skip_configurebool
Skip configure. Default False.
- skip_compilebool
Skip make ACoreChip. Default False.
- class acorechip.acore_compilers.ACoreSWCompiler(*arg, **kwargs)
Class for compiling sources for A-Core
Parameters
- test_configdict
A-Core test config
- hw_configdict
A-Core hw config
- acore_lib_pathstr
Path to ACore library
- acore_headers_pathstr
Path to ACore header files
- platformstr
Target platform (sim, fpga)
- make_argsdict
Arbitrary make parameters to propagate
- skip_cleanbool
Skip make clean. Default False.
- skip_compilebool
Skip compile. Default False.
- target_dirstr
Target directory for elf file
Example
compiler = ACoreSWCompiler(...) compiler.init() compiler.run()
- property bin
Path to compiled elf file.
- check_none()
Check if any attribute is None.
- clean()
Run
make clean.
- compile()
Run
maketo compile the software program.
- compose_clean_cmd()
Compose
make cleancommand.
- compose_compile_cmd()
Compose
makecommand to compile software program.
- init()
Initialize compiler.
- parse_options()
Parse options.
- run()
Run compiler.
- class acorechip.config.ACoreTestConfig(**kwargs)
Class for loading ACore test configurations.
Parameters
- config_pathstr
Absolute path to the test config
- replace_listdict
Replacement list to replace an entry from the loaded yaml. Key indicates the entry to be replaced, and value the new value.
- init()
Initialize.
- load_config_yaml(filepath)
Recursively load test configuration from yaml configuration files.
Keys ending with
_yamlcontain paths to yaml configuration files. The contents of these files are loaded to keys without the suffix.For example, the contents of
hw_config_yamlare loaded into dictionary corresponding to keyhw_config.If both
sim_config_yamlandsim_configexists, the latter is used to override values provided in the former. This allows usingsim_config_yamlas a template, while you can still modify individual parameters on test-level.
- print_config()
Print the config that was loaded.
- replace_constants(config)
Replace constant values in a config file.
- run()
Run config loader.
- class acorechip.controller.controller(dut, **kwargs)
A-Core controller.
This class defines simulation-related things, such as the input IOs, reset sequence, simulation stop.