Testbench Classes

class acoretestbenches.generic_sim_testbenches.GenericTestbench(**kwargs)

Abstract class for testbenches. Extend your custom testbench with this class or its child class.

Example

class CustomTestbench(GenericTestbench)

Parameters

test_configdict

Test configuration

test_namestr

Optional name for the test

cache_dirstr

Path to the cache directory. By default it is under .cache

init()

Default generic init function. Use this in your custom testbench by calling super().init().

init_cache_locations()

Defines the cache location for cached chisel products.

init_compilers()

Initialize compilers.

init_dut()

Initialize ACoreChip TheSydekick module.

init_jtag()

Initialize JTAG.

init_properties()

Initialize generic properties.

load_configs()

Load configuration files from self.test_config.

run()

Default generic run function. Runs chisel and sw compilers and creates symbolic links to rtl simulation folder under Entities/acorechip/simulations. Use this in your custom testbench by calling super().run().

Symlink source RTL files from chisel cache dir to RTL simulation folder. RTL simulation folder is typically located under Entities/acorechip/simulations.

class acoretestbenches.generic_sim_testbenches.GenericTheSydekickSimTestbench(**kwargs)

Testbench class for running simulations using TheSydeKick framework.

Example

sdk_tb = GenericTheSydekickSimTestbench()
sdk_tb.init()
sdk_tb.run()

See sim_configs/thesdk.yml for explanations on different parameters.

define_sim_flow()

Define simulation flow.

generate_jtag_stream()

Generate JTAG stream. Store it in jtag_tap_in IO.

init(**kwargs)

Default generic init function. Use this in your custom testbench by calling super().init().

init_dut_controller()

Initialize ACoreChip controller.

init_simulator()

Initialize simulator.

run()

Default generic run function. Runs chisel and sw compilers and creates symbolic links to rtl simulation folder under Entities/acorechip/simulations. Use this in your custom testbench by calling super().run().

class acoretestbenches.generic_sim_testbenches.GenericCocotbSimTestbench(**kwargs)

Testbench class for running simulations using cocotb framework.

Example

cocotb_tb = GenericCocotbSimTestbench()
cocotb_tb.init()
cocotb_tb.run()

See sim_configs/cocotb.yml for explanations on different parameters.

cocotbify()

“cocotbify” the verilog - allows generating VCD trace of the simulation. Needed for icarus runs.

compose_args()

Compose simulation and compilation arguments for cocotb.

generate_jtag_stream()

Generate JTAG stream and save it in a tempfile.

init()

Default generic init function. Use this in your custom testbench by calling super().init().

init_simulator()

Initialize simulator.

postsim_logs()

Prints a command for opening waveform file after simulation ends.

run()

Default generic run function. Runs chisel and sw compilers and creates symbolic links to rtl simulation folder under Entities/acorechip/simulations. Use this in your custom testbench by calling super().run().

run_cocotb()

Run cocotb testbench.