Simulation config

Simulation parameters are handled with simulation configuration YAML files. The config is automatically read by ACoreTestConfig and turned into a dictionary, accessible from the testbench in self.sim_config.

Example sim config: thesdk.yml

# Template for running GenericTheSydekickSimTestbench

# Testbench module - the Python module where the testbench exists
tb_module: acoretestbenches.generic_sim_testbenches

# Testbench class - the Python class name of your testbench
tb_class: GenericTheSydekickSimTestbench

# Simulator - icarus and questa are supported
# Use questa if possible - it's much faster
backend: icarus

# Selfchecking - if your code uses `test_pass()` and `test_fail()` library functions
selfchecking: true

# Simulation timeout - when does simulation stop. Unit: clock cycles.
# Counting start after JTAG programming finishes.
timeout: 50000000

# Interactive RTL - i.e. whether to open waveform file after simulation
interactive_sim: true

# Skip JTAG programming sequence and initialize the memories
skip_jtag_prog: true

# Interactive controlfile for waveform viewer
interactive_controlfile: $ACORECHIP/interactive_control_files/gtkwave/general.tcl # icarus
#interactive_controlfile: $ACORECHIP/interactive_control_files/modelsim/dofile.do # questa
#interactive_controlfile: $ACORECHIP/interactive_control_files/modelsim/dofile_minimal.do # questa with sim_opt == fast
#interactive_controlfile: $ACORECHIP/interactive_control_files/modelsim/dofile_multicore.do #questa for dual-core system

# Simulation option for QuestaSim
# log_all, fast
sim_opt: log_all

# When sim_opt == fast, define modules whose signals you want kept
# tb_acorechip and acorechip needed for simulation stimuli
# ControlStatusRegs needed for mstopsim
opt_keep_modules: ["tb_acorechip", "acorechip", "ControlStatusRegs"]

# Clock frequency of the main clock in Hz
clock_freq: 100_000_000

# Clock frequency for JTAG TCK
jtag_clock_freq: 10_000_000

# Use a cached chisel version, if exists, instead of compiling anew
use_cached_chisel: false

# Platform - sim for simulations, fpga for measurements
platform: sim

# Skip software compile and use a previously compiled version
skip_sw_compile: false

# Preserve rtl files in simulation folder after simulation
preserve_rtlfiles: false

# Preserve iofiles in simulation folder after simulation
preserve_iofiles: false

# RTL timescale for the simulation
rtl_timescale: 1ps

# RTL timeprecision for the simulation
rtl_timeprecision: 1ps