Cocotb Testbenches

acoretestbenches.test_cocotb.test_acorechip(dut)

This test loads the program from an elf file into ROM, toggles reset, and runs the clock for a specified number of clock cycles.

A-Core’s mstopsim CSR is monitored - once its 0th bit is set to 1, simulation is stopped. Simulation result is stored in its 1st bit. Otherwise, a timeout value is used. If the test is set as selfchecking (i.e. it writes to mstopsim), and timeout is reached, cocotb throws a SystemError. An AssertionError is thrown if mstopsim 1st bit is 0 after simulation is stopped.

This testbench uses JTAG to set A-Core’s core_en because, with verilator, it is not possible to write to internal signals (except memory, seemingly).

acoretestbenches.test_cocotb_spike.test_acorechip(dut)

This test is similar to acoretestbenches.test_cocotb.test_acorechip, but it runs the Spike simulator in parallel. Every time an instruction is retired, the program counter and register values are compared between A-Core and Spike. If there is a mismatch, simulation is halted.

The test generates a logfile sim.log. It is generated to the location where this module was called, so most likely Entities/acoretests/acoretests.